LoMoSA+

The LoMoSA project aims at the creation of a low-power expertise for mobile and multimedia applications by initiating the development of a European low-power System-on-Chip (SoC) platform.
It consists of an interacting combination of (architectural) models, design flows and methodologies, hardware design components, embedded software and test-benches. The project investigates low-power solutions for bus-controlled SoCs, but also covers the impact on power, scalability and performance of future multiprocessor SoC infrastructures based on novel on-chip communication solutions.
LoMoSA brings together world-class experts from the industry (NXP, STMicroelectronics, Thales, Thomson), university research labs and institutes (CEA-LETI, CEA-LIST, TIMA, ALaRI, University of Cantabria) and 1 SME's (DS2).

LoMoSA+ Work-packages

The LoMoSA activities have been subdivided into 5 Workpackages, of which the contents are described below:

WP1:

The WP1 workpackage targets the identification and the specification of the architectural templates for advanced multimedia and low-power applications and especially targeting next generation portable video, GSM/EDGE and DVB-H mobile terminal solutions.
This activity will cover both architectural and micro-architectural aspects (e.g. symmetric or heterogeneous multiprocessor configuration, number and purpose of each processor core etc.) as well as the actual definition of the application service to be delivered (e.g. 3D enhancements). The architectural platform to be developed will be suitable for a variety of standards and future applications.
The outcomes of WP1, where all LoMoSA Partners are directly or indirectly involved, give the constraints for the development of the platform components that are generated in WP2, WP3 and WP4. The final report of the WP1 describes possible templates for mobile multimedia and low-power platforms that is feasible within (the limitations of) LoMoSA and the roadmap to come to further extension of such Low-Power platforms.

WP2:

In WP2 advanced functional blocks are designed to generate the hardware components for the low-power platform. Boundary conditions (e.g. Low-power interface standards) will conform to the results of WP1. A number of activities in WP2 are strongly linked to software-related activities in WP3, e.g. power and functional modelling is needed to allow for profiling of embedded software running on processor cores.
Furthermore most of the IP blocks that will be developed in WP2 have a direct relation to one of the LoMoSA application demonstrators, described in WP5 (TV-in-Mobile receiver and portable video mobile terminal).
The HW components concern a number of basic building blocks (e.g. for a DVB-T/H mobile TV receiver) and library blocks for utilization of low-power techniques.
All above-mentioned hardware components are targeted for implementation in a 65nm CMOS technology (or beyond). However, practical reasons could ask for a first implementation of some of the blocks in an earlier technology (e.g. 90 nm).

WP3:

WP3 is focused on the HdS (Hardware-dependent Software) and RTOS (Real-time Operating System) inside a MPSOC (Multi-processor System-on-Chip), and two main aspects: Multi-Processing support and Low-Power constraints. A virtual prototype is used to validate hardware related RTOS functionalities, like power-awareness, and HdS libraries.
Run-time power management by development of a set of RT-OS driven control techniques will optimise average power consumption (dynamic and static) and thus extends battery life. Finding the optimal control technique for selective shutdown, frequency settings, voltage scaling and trade-off between open-loop and closed-loop power control policies is a ‘hot topic’ and can result in relatively high power savings.
WP3 is composed of three main tasks: 

– HdS for MPSoC modelling
– RTOS enhancement for Power awareness, Multi-Processor support (Scheduling, Cache, Coherency, Interrupt, …)
– HdS-based design tools for MPSoC with NoC

WP4:

The objectives of WP4 are design methods, which allow for an early system verification, performance analysis, and power estimation preferably at system level. An important activity in WP4 concerns the development of tools at each of the design levels, from system specification over architecture and software design, to circuit level. For that reason WP4 is composed of 5 main tasks, covering the following topics:

– Verification and validation methodology and tools
– High-level power estimation and system simulation methodologies
– Low power memory, communication and interface design
– Low power software compilation and high-level synthesis
– Low-power logic and circuit design

WP5:

The objective of work package 5 is to demonstrate what has been developed in common within LoMoSA to reduce drastically power consumption of next generation of deep submicron technologies in the particular field of mobile and multimedia applications.
Work package 5 is divided in three main tasks: 

– Low Power Mobile and Multimedia system demonstrator
– HdS (Hardware Dependent Software) and RT-OS (Real Time Operating System) technology demonstrator system
– Powerline and HdS technology demonstrator